1. Field of the Invention
The present invention relates generally to program execution control devices for storing instructions in an instruction storage device and designating addresses of the device to read the instructions in a specific order and apply the same to a program execution device and a method thereof. More particularly, the present invention relates to a program execution control device which is capable of performing such instruction reading at high speed while requiring a relatively small-scale circuit and a method thereof, and a program conversion method for converting a program into a form readable by such a program execution control device and by such a method.
2. Description of the Related Art
FIG. 1 shows an example of a conventional program execution control device (hereinafter referred to as a "program control unit") for controlling a program execution order in a microprocessor or the like. With reference to FIG. 1, a conventional program control unit includes a program counter (PC) 300, an instruction memory 32, an instruction decoder 34, an incrementer 302 and a selector 304.
Instruction memory 32 stores instructions of a program in the order of program addresses. Program addresses are ordinarily set to be incremented one by one. In instruction memory 32, the program addresses are arranged in a continuous memory space whose addresses are incremented one by one. Instruction memory 32 is for reading an instruction word 38 (of m-bit) from an applied n-bit address 310 and applying the word to instruction decoder 34.
Instruction decoder 34 is for decoding m-bit instruction word 38 to apply an l-bit control signal 40 according to the instruction to an execution device such as an arithmetic logic unit. Instruction decoder 34 also decodes an instruction word to output a select signal 42, a jump address and the like to selector 304.
Selector 304 is for selecting either an n-bit output 306 from incrementer 302 or n-bit jump address 44 from instruction decoder 34 in response to select signal 42 applied from instruction decoder 34 to apply the selected output or address as an output 308 (of n-bit) to program counter 300.
Program counter 300 is for outputting address 310 for the read of an instruction word from instruction memory 32. Output 310 of program counter 300 is applied also to incrementer 302.
Incrementer 302 is for incrementing (adding 1) to the contents of program counter 300 and applying n-bit output 306 to selector 304.
The program control unit shown in FIG. 1 operates as follows. First, program counter 300 is set to 0 through reset operation or the like. With output 310 of program counter 300 as an address, an instruction of instruction memory 32 at address 0 is read as instruction word 38. The read instruction word 38 is decoded by instruction decoder 34 and select signal 42, control signal 40, jump address 44 and the like are output.
Output 310 of program counter 300 is at the same time applied to incrementer 302, incremented there and applied to selector 304. When select signal 42 from instruction decoder 34 controls selector 304 so as to select the output of incrementer 302, selector 304 selects output 306 of incrementer 302 and applies the same to program counter 300. As long as select signal 42 has a value for selecting the output of incrementer 302, therefore, output 310 of program counter 300 is incremented one by one.
When an instruction decoded by instruction decoder 34 is a branch instruction, instruction decoder 34 outputs jump address 44, as well as applying select signal 42 for controlling selector 304 so as to select jump address 44 to selector 304. Selector 304 selects jump address 44 and applies the same to program counter 300. In this case, therefore, the value of program counter 300 is set to the jump address.
Although FIG. 1 shows only a schematized simple example, call addresses, return addresses, interrupt addresses etc. of a sub-routine other than those shown in the figure are to be selected by selector 304 in practice.
FIG. 2 shows a flow chart for down-loading a program into instruction memory 32 shown in FIG. 1. First at Step 90, programs are produced with a high-level language. These high-level language programs are converted into a machine language by an assembler, a linker and a compiler, while addresses are assigned to the instruction memory at Step 92. At Step 96, the program converted into a machine language is loaded into a real memory (instruction memory). Arrangement of instructions in the real memory in this case will be described later with reference to FIG. 3. Further at Step 320, the program arranged on the real memory is executed by a program counter.
FIG. 3 is an arrangement of program addresses on the real memory at the time of the program loading into the real memory at Step 96 shown in FIG. 2. With reference to FIG. 3, assuming that there are 127 instructions included in the program converted into the machine language by an assembler, a linker and a compiler, these instructions are referred to as instructions 1 to 127. Program addresses 0-126 are respectively assigned to these instructions. When the program is loaded into the real memory, the program address of each instruction will be an address incremented one by one with respect to the leading instruction 1 in the order of the original program addresses in the range from 0 to 126.
A conventional program control device requires an incrementer for incrementing a program counter. Increment processing inevitably involves addition processing. Delay caused by carry involved in addition processing reduces an operating speed of the incrementer. In view of a need for enhancing an operating speed of processors, it is not desirable to use such an incrementer slow in operation.
On the other hand, to increase a speed of addition processing, proposed in Japanese Patent Laying-Open No. 1-193931 for example, is a technique for speeding up operation of an incrementer by dividing the incrementer into a plurality of blocks and providing a carry control circuit for each block to generate a carry on a block basis to reduce a propagation delay caused by the carry. Such a device, however, has drawbacks that a circuit of an incrementer is increased in scale and improvement of an operating speed fails to offset an increase of a circuit in scale. In order to solve these problems, it is desirable to read instructions at high speed through effective use of a memory even when a large-scale program or numerous programs are executed.